Band gap tailoring for a tunneling dielectric for a three-dimensional memory structure

US9449980B2 · kind B2 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventor

• Peter Rabkin · Cupertino, US

Key dates

• Filing date: Oct 31, 2014
• Grant date: Sep 20, 2016
• Expiry date: Oct 31, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/118

Abstract

The band gap structure of a tunneling dielectric can be tailored to facilitate programming and erasing of stored information, while enhancing charge storage during states without electrical bias between a semiconductor channel and charge storage elements. The tunneling dielectric includes a layered stack including at least, from outside to inside, a dielectric metal oxide layer and a silicon oxide layer. Upon application of electrical bias for programming or erasing, the band gap structure of the tunneling dielectric provides a lower tunneling barrier than an ONO stack of a comparable effective oxide thickness. Additionally, due to higher capacitive coupling to the channel with high-k metal oxide layer(s) in the tunneling dielectric, the efficiency of program, erase and read operations can be improved. During a zero-bias state, the tunneling dielectric can provide a higher energy barrier than the ONO stack, thereby providing enhanced data retention than the ONO stack.