Through silicon via device having low stress, thin film gaps and methods for forming the same
US9455188B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Jan 18, 2013 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.