Semiconductor apparatus having TSV and testing method thereof
US9455190B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Aug 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test method of a semiconductor apparatus before a wafer is ground may include applying voltages to a bump electrically coupled to a through-silicon via (TSV) which is buried in the wafer and a first conductive layer formed to be electrically connected to a rear surface of the TSV, wherein the first conductive layer is withdrawn into an upper surface of the wafer. The method may include measuring a voltage between the bump and the first conductive layer. The method may include comparing the measured voltage to a preset reference voltage. The method may include determining the TSV as a normal TSV in which no fail occurs, according a comparing result, and grinding the wafer to expose the rear surface of the TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.