Patent · US Active

Multiple depth vias in an integrated circuit

US9455312B2 · kind B2 · utility

5Cited by
2References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 23, 2015
Grant dateSep 27, 2016
Priority date—
Expiry dateNov 23, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.