Standard cell library with DFM-optimized M0 cuts and V0 adjacencies
US9461065B1 · kind B1 · utility
9Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | Apr 17, 2016 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.