Jonathan Haigh
95Patents
7h-index
27Co-inventors
64Inventor score
Filing activity: Apr 19, 2013 → Jun 30, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9799575B2 | Integrated circuit containing DOEs of NCEM-enabled fill cells | Electricity | 17 | Active |
| US9805994B1 | Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads | Electricity | 13 | Active |
| US9870962B1 | Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Electricity | 12 | Active |
| US9595536B1 | Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies | Electricity | 12 | Active |
| US9627370B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 11 | Active |
| US9461065B1 | Standard cell library with DFM-optimized M0 cuts and V0 adjacencies | Electricity | 9 | Active |
| US10593604B1 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells | Electricity | 8 | Active |
| US9529954B1 | Standard cell library with DFM-optimized M0 cuts | Electricity | 7 | Active |
| US9627371B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 5 | Active |
| US9202820B1 | Flip-flop, latch, and mux cells for use in a standard cell library and integrated circuits made therefrom | Emerging Cross-Sectional Technologies | 5 | Active |
| US10978438B1 | IC with test structures and E-beam pads embedded within a contiguous standard cell area | Electricity | 4 | Active |
| US9691672B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Electricity | 4 | Active |
| US9627408B1 | D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies | Electricity | 3 | Active |
| US10096530B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells | Electricity | 3 | Active |
| US9438237B1 | High-yielding standard cell library and circuits made therefrom | Electricity | 3 | Active |
| US9773774B1 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells | Electricity | 3 | Active |
| US9741703B1 | Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells | Electricity | 3 | Active |
| US9704846B1 | IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same | Electricity | 3 | Active |
| US10199283B1 | Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage | Electricity | 3 | Active |
| US9911649B1 | Process for making and using mesh-style NCEM pads | Electricity | 2 | Active |
| US9786648B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9761575B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9984970B1 | Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs | Emerging Cross-Sectional Technologies | 2 | Active |
| US9653446B1 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells | Electricity | 2 | Active |
| US9748153B1 | Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.