Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same
US9461114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82B3/0014
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.