Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same
US9461149B2 · kind B2 · utility
11Cited by
1References
15Claims
0Family size
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Key dates
| Filing date | Sep 12, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.