Multi processor multi domain conversion bridge with out of order return buffering
US9465741B2 · kind B2 · utility
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Key dates
| Filing date | Oct 17, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Nov 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.