Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
US9465767B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.