Patent · US Active

Systems and methods for testing integrated circuit designs

US9465896B1 · kind B1 · utility

3Cited by

0References

13Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Paul Alexander Cunningham · San Jose, US
Steev Wilcox · San Jose, US
Vivek Chickermane · Ithaca, US

Key dates

Filing date	Mar 4, 2015
Grant date	Oct 11, 2016
Priority date	—
Expiry date	Mar 4, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/333
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.