Methods and circuits for securing proprietary memory transactions
US9465961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jun 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/56
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.