Row decoder for non-volatile memory devices and related methods
US9466347B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.