Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process
US9466538B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a sur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.