Split-gate memory cell with depletion-mode floating gate channel, and method of making same
US9466732B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2012 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Aug 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.