Method for dividing testable logic into a two-dimensional grid for physically efficient scan
US9470755B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318335
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.