Method for using sequential decompression logic for VLSI test in a physically efficient construction

US9470756B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Steev Wilcox · San Jose, US
• Brian Foutz · Charlottesville, US
• Krishna Vijaya Chakravadhanula · Vestal, US
• Vivek Chickermane · Ithaca, US
• Paul Alexander Cunningham · San Jose, US

Key dates

• Filing date: Jun 12, 2015
• Grant date: Oct 18, 2016
• Expiry date: Jun 12, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318583
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.