Resistive switching memory with cell access by analog signal controlled transmission gate
US9472272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Feb 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.