Methods of fabricating integrated circuits
US9472465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | May 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.