Self aligned embedded gate carbon transistors
US9472640B2 · kind B2 · utility
2Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Apr 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.