Patent · US Active

ASIC element, in particular as a component of a vertically integrated hybrid component

US9475693B2 · kind B2 · utility

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9Claims
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Assignee

Inventors

Key dates

Filing dateJun 8, 2015
Grant dateOct 25, 2016
Priority date
Expiry dateJun 8, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/1461
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.