Debug circuit for an integrated circuit

US9476937B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Garima Sharda · Ghaziabad, IN
• Sunny Gupta · Noida, IN
• Akshay K. Pathak · Noida, IN
• Nidhi Sinha · Noida, IN

Key dates

• Filing date: Oct 15, 2014
• Grant date: Oct 25, 2016
• Expiry date: Jul 23, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31705
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.