Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory
US9478273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2013 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1697
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.