Shallow trench isolation structures in semiconductor device and method for manufacturing the same
US9478457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2015 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.