Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device

US9478544B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Jerome Mitard · Bossut-Gottechain, BE
• Roger Loo · Leuven, BE
• Liesbeth Witters · Linden, BE

Key dates

• Filing date: Jul 24, 2015
• Grant date: Oct 25, 2016
• Expiry date: Jul 24, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/405
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.