Uncore microcode ROM
US9483263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2013 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jan 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30174
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.