Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features
US9484076B1 · kind B1 · utility
24Cited by
10References
50Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Oct 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.