Dual polarity read operation
US9484089B2 · kind B2 · utility
7Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Feb 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.