Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same
US9484252B2 · kind B2 · utility
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2References
19Claims
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Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jul 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed. An ILD layer is deposited overlying the metal capping layer and the exposed portions of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.