Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers
US9484449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.