Hoon Kim
196Patents
20h-index
174Co-inventors
93Inventor score
Filing activity: Dec 28, 1999 → Feb 3, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9876651B2 | Home appliance and home network system using the same | Physics | 183 | Active |
| US9012319B1 | Methods of forming gate structures with multiple work functions and the resulting products | Electricity | 71 | Active |
| US7423991B2 | Apparatus and method for allocating subchannels adaptively according to frequency reuse rates in an orthogonal frequency division multiple access system | Electricity | 68 | Active |
| US9847390B1 | Self-aligned wrap-around contacts for nanosheet devices | Electricity | 57 | Active |
| US9780208B1 | Method and structure of forming self-aligned RMG gate for VFET | Electricity | 49 | Active |
| USD624957S1 | Copy machine | General | 40 | Expired |
| USD641395S1 | Printer | General | 40 | Expired |
| USD624956S1 | Copy machine | General | 39 | Expired |
| US9508604B1 | Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers | Electricity | 38 | Active |
| USD641038S1 | Printer | General | 38 | Expired |
| US9799748B1 | Method of forming inner spacers on a nano-sheet/wire device | Electricity | 31 | Active |
| USD641396S1 | Printer | General | 29 | Expired |
| USD641393S1 | Printer | General | 26 | Expired |
| US7961651B2 | Method and system for managing energy in sensor network environment using spanning tree | Electricity | 26 | Active |
| US9780197B1 | Method of controlling VFET channel length | Electricity | 25 | Active |
| US8208887B2 | Receiving circuit including balun circuit and notch filter and operating method thereof | Electricity | 24 | Active |
| US6349103B1 | Cold-start wavelength-division-multiplexed optical transmission system | Electricity | 23 | Expired |
| USD647131S1 | Laser printer | General | 22 | Expired |
| US7310023B2 | Frequency synthesizer | Electricity | 22 | Active |
| US7932176B2 | Self-aligned barrier layers for interconnects | Electricity | 20 | Active |
| US9178036B1 | Methods of forming transistor devices with different threshold voltages and the resulting products | Electricity | 19 | Active |
| US9337101B1 | Methods for selectively removing a fin when forming FinFET devices | Electricity | 18 | Active |
| US9761495B1 | Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices | Electricity | 17 | Active |
| US7660531B2 | Remote access unit and radio-over-fiber network using same | Electricity | 16 | Active |
| US8222134B2 | Self-aligned barrier layers for interconnects | Electricity | 15 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.