Techniques for compiling and generating a performance analysis for an integrated circuit design
US9489480B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jan 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.