Integrated circuits having improved gate structures and methods for fabricating same
US9490129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.