Method of fabricating semiconductors
US9490143B1 · kind B1 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.