Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects
US9494647B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Dec 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of data inversion, circuitry, detection and/or schemes are disclosed. According to illustrative implementations, exemplary circuitry may include static detection or detection circuitry such as those involving static current sources to detect a threshold for data inversion, pre-conditioning of detection circuitry, and/or active detection circuitry or schemes. In some implementations, exemplary memory or data inversion circuitry may comprise a transistor array, a bias generator, and a sense amplifier, wherein the transistor array may comprise at least one pair of transistor circuits arranged so that an output of the transistor array is provided as a sum or function of signal/current outputs of at least some of the transistor circuits in the array. As set forth, various systems, methods and circuitry herein may posses only a 3 static gate delay, such that very high speed and/or fast flow-through is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.