Reset circuitry for integrated circuit
US9494969B2 · kind B2 · utility
2Cited by
2References
11Claims
0Family size
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Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.