Forcing core low power states in a processor
US9495001B2 · kind B2 · utility
4Cited by
26References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2013 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Nov 28, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.