Power reduction in thyristor random access memory
US9496021B2 · kind B2 · utility
4Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Aug 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.