Method of charge controlled patterning during reactive ion etching
US9496148B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Sep 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of reactive ion etching a wafer includes providing a plasma processing tool having a wafer chuck within a chamber and an electrode creating a plasma above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer. Both p− and n+ layers have exposed peripheral edges during plasma etching to electrically form with the plasma processing tool during plasma etching a diode having an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge. The method includes controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer edge, and reactive ion etching the n+ layer while controlling the charge flow along the edge of the n+ layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.