Microprocessor with ALU integrated into load unit
US9501286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jul 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.