Configurable peripheral componenent interconnect express (PCIe) controller
US9501442B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.