Stress compensation layer for 3D packaging
US9502360B2 · kind B2 · utility
10Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2012 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jan 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.