Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

US9502363B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Michael B. Vincent · Chandler, US
• Trung Q. Duong · Austin, US
• Zhiwei Gong · Chandler, US
• Scott M. Hayes · Chandler, US
• Alan J. Magnus · Gilbert, US
• Douglas G. Mitchell · Tempe, US
• Eduard Jan Pabst · Mesa, US
• Jason Wright · Sunnyvale, US
• Weng F. Yap · Phoenix, US

Key dates

• Filing date: Mar 24, 2014
• Grant date: Nov 22, 2016
• Expiry date: Mar 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.