Semiconductor structure and manufacturing method thereof
US9502410B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jul 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.