Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising an NMOS device and a PMOS device

US9502415B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Roger Loo · Leuven, BE
• Jerome Mitard · Bossut-Gottechain, BE
• Liesbeth Witters · Linden, BE

Key dates

• Filing date: Jul 24, 2015
• Grant date: Nov 22, 2016
• Expiry date: Jul 24, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is und…