Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control

US9502521B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Udayan Ganguly · San Jose, US
• Christopher S. Olsen · Fremont, US
• Sean M. Seutter · Fremont, US
• Lucien Date · Ottignies, BE

Key dates

• Filing date: Jul 22, 2011
• Grant date: Nov 22, 2016
• Expiry date: Dec 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693

Abstract

A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.