Integrated fabrication of semiconductor devices
US9502556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Feb 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.