Decoupled selective implementation of entry and exit prediction for power gating processor components
US9507410B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jun 20, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.