Patent · US Active

Sharing program interrupt logic in a multithreaded processor

US9507602B2 · kind B2 · utility

4Cited by

1References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Khary J. Alexander · Poughkeepsie, US
Michael Billeci · Poughkeepsie, US
Fadi Y. Busaba · Poughkeepsie, US
Mark S. Farrell · Pleasant Valley, US
Christian Jacobi · West Park, US
Timothy J. Slegel · Staatsburg, US

Key dates

Filing date	Mar 28, 2016
Grant date	Nov 29, 2016
Priority date	—
Expiry date	Mar 28, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/5005
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.