Hierarchical FTL mapping optimized for workload
US9507711B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2015 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory system having non-volatile memory and volatile memory, write data are stored in a write-coalescing buffer in the volatile memory until the write data is written to non-volatile memory. First and second level address mapping tables are stored in the volatile memory and corresponding first and second level address mapping tables are stored in the non-volatile memory, and furthermore the second level address mapping table in the volatile memory contains entries corresponding to only a subset of the entries in the second level address mapping table in the non-volatile memory. The first address-mapping table in volatile memory includes entries storing pointers to entries in the second address-mapping table in volatile memory, entries storing pointers to locations in the write-coalescing buffer, and entries storing pointers to locations in the non-volatile memory that store data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.